1. Field of the Invention
The present invention relates to a microcomputer having an on-screen display in which a processing time required for a central processing unit is shortened to improve a software processing efficiency.
2. Description of Related Art
FIG. 11 is a block diagram showing the configuration of a conventional microcomputer having an on-screen display.
As shown in FIG. 11, a reference numeral 113 indicates a data storing unit including a read only memory (ROM) and a random access memory (RAM), and data used in the conventional microcomputer is stored in the data storing unit 113. A reference numeral 114 indicates an on-screen display (OSD) RAM, and display data to be displayed on a cathode ray tube (CRT and not shown) is stored in the OSD-RAM 114.
A reference numeral 111 indicates a central processing unit (CPU), and the conventional microcomputer is controlled by the CPU 111. The accessing of the CPU 111 to the data storing unit 113 or the accessing of the CPU 111 to the OSD-RAM 114 is performed according to a data read/write request of the CPU 111 to perform a data reading or writing from/to the data storing unit 113 or to perform a display data writing to the OSD-RAM 114. A reference numeral 115 indicates a 1-wait register, and an access mode value xe2x80x9c0xe2x80x9d indicating a no-wait access mode or an access mode value xe2x80x9c1xe2x80x9d indicating a 1-wait access mode is stored in the 1-wait register 115 according to an access mode instruction transmitted from the CPU 111.
A reference numeral 112 indicates a bus interface unit (BIU). The BIU 112 controls the data read/write request transmitted from the CPU 111 to be transmitted to the data storing unit 113 or the OSD-RAM 114. Also, the BIU 112 sets an access mode (for example, the no-wait access mode denoting a shortest access cycle or the 1-wait access mode denoting a double access cycle) of the conventional microcomputer according to the access mode value of the 1-wait register 115 to transmit the data read/write request of the CPU 111 to the data storing unit 113 or the OSD-RAM 114 and to make the CPU 111 access to the data storing unit 113 or the OSD-RAM 114 at the access mode.
A reference numeral 116 indicates an OSD logical circuit. An OSD-RAM read request signal S2 of the OSD logical circuit 116 is transmitted to the OSD-RAM 114 to access to the OSD-RAM 114 at the access mode set by the BIU 112 to read out the display data stored in the OSD-RAM 114.
A reference numeral 118 indicates a change-over switch, and a connection between the CPU 111 and the OSD-RAM 114 or a connection between the OSD logical circuit 116 and the OSD-RAM 114 is selected by the change-over switch 118 according to the data read/write request of the CPU 111 or the OSD-RAM read request signal S2 of the OSD logical circuit 116.
A reference numeral 117 indicates an address/data bus, and data read out or written from/in the data storing unit 113, the data read/write request of the CPU 111 and the access mode value requested by the CPU 111 transmit through the address/data bus 117.
An on-screen display of the conventional microcomputer is composed of the OSD-RAM 114, the OSD logical circuit 116 and the change-over switch 118.
In the above configuration, an operation of the conventional microcomputer is described.
FIG. 12 is a timing chart of signals used in the operation of the conventional microcomputer having the on-screen display.
When an access mode instruction is transmitted from the CPU 111 to the 1-wait register 115 through the BIU 112, an access mode value xe2x80x9c0xe2x80x9d or an access mode value xe2x80x9c1xe2x80x9d is stored in the 1-wait register 115 under control of the BIU 112, and an access mode of the conventional microcomputer is set by the BIU 112 according to a 1-wait signal Sw transmitted from the 1-wait register 115. In cases where the access mode value xe2x80x9c0xe2x80x9d is set in the 1-wait register 115, the BIU 112 sets a no-wait access mode denoting a shortest access cycle, so that an access of the CPU 111 to the ROM-RAM 113 or the OSD-RAM 114 is performed at the shortest access cycle. That is, no wait time is required of the CPU 111. In contrast, in cases where the access mode value xe2x80x9c1xe2x80x9d is set in the 1-wait register 115, the BIU 112 sets a 1-wait access mode denoting a double access cycle, so that an access of the CPU 111 to the ROM-RAM 113 or the OSD-RAM 114 is performed at the double access cycle which is two times of the shortest access cycle.
Thereafter, when a data read/write request is transmitted from the CPU 111 to the data storing unit 113 under control of the BIU 112, the accessing of the CPU 111 to the data storing unit 113 is performed at the access mode set by the BIU 112. Also, when a data read/write request is transmitted from the CPU 111 to the change-over switch 118 under control of the BIU 112, the change-over switch 118 connects the CPU 111 with the OSD-RAM 114, and the accessing of the CPU 111 to the OSD-RAM 114 is performed at the access mode set by the BIU 112.
Also, when an OSD-RAM read request signal S2 is transmitted from the OSD logical circuit 116 to the change-over switch 118 in synchronization with vertical and horizontal synchronization signals transmitted from the outside at a time that an CRT of the on-screen display is operated, the change-over switch 118 connects the OSD logical circuit 116 with the OSD-RAM 114, the accessing of the OSD logical circuit 116 to the OSD-RAM 114 is performed at the access mode set by the BIU 112, and the display data of the OSD-RAM 114 is read out to the OSD logical circuit 116. Therefore, a display signal is produced in the OSD logical circuit 116 according to the display data, and the display signal is transmitted to the CRT in synchronization with the vertical and horizontal synchronization signals.
However, in cases where the OSD logical circuit 116 accesses to the OSD-RAM 114 when the CPU 111 accesses to the OSD-RAM 114 at the no-wait access mode, because the CPU 111 and the OSD logical circuit 116 cannot simultaneously access to the OSD-RAM 114, there is a problem that a wrong operation is performed in the conventional microcomputer.
To avoid this problem in the conventional microcomputer, the access mode value xe2x80x9c1xe2x80x9d indicating the 1-wait access mode is set in the 1-wait register 115 during the operation of the on-screen display, and the CPU 111 and the OSD logical circuit 116 access to the OSD-RAM 114 in time-division at the double access cycle. For example, as shown in FIG. 12, when the operation of the on-screen display is started at a time T100, the access mode value xe2x80x9c1xe2x80x9d is set in the 1-wait register 115 to transmit a 1-wait signal Sw of a high level to the BIU 112, and the conventional microcomputer is set to the 1-wait access mode. Thereafter, in cases where the accessing of the CPU 111 to the OSD-RAM 114 and the accessing of the OSD logical circuit 116 to the OSD-RAM 114 are simultaneously performed in a time-period T100 of one double access cycle by transmitting a CPU access address of the data read/write request indicating the OSD-RAM 114 and an OSD-RAM read request signal S2 of the OSD logical circuit 116 to the change-over switch 118, the CPU 111 accesses to the OSD-RAM 114 during a first half time-period T121 of the time-period T100, and the OSD logical circuit 116 accesses to the OSD-RAM 114 during a second half time-period T122 of the time-period T100.
However, because the conventional microcomputer is set to the 1-wait access mode during the operation of the on-screen display, a time-period of each access of the CPU 111 to the data storing unit 113 or the OSD-RAM 114 is doubled to two clocks of a system clock signal during the operation of the on-screen display as compared with that at the no-wait access mode. For example, when the CPU 111 accesses to the data storing unit 113 during the operation of the on-screen display, the accessing of the CPU 111 is performed at the 1-wait access mode. Therefore, there is a drawback that a memory processing speed of the CPU 111 is lowered to half during the operation of the on-screen display so as to lower a software processing efficiency.
An object of the present invention is to provide, with due consideration to the drawback of the conventional microcomputer having the on-screen display, a microcomputer having an on-screen display in which a software processing efficiency is improved while allowing the simultaneous accessing of a CPU and an OSD logical circuit to an OSD-RAM.
The object is achieved by the provision of a microcomputer having an on-screen display, comprising:
a first register for registering an access mode value indicating a first access mode corresponding to a first bus cycle or a second access mode corresponding to a second bus cycle longer than the first bus cycle;
a first storing circuit for storing first data;
a display data storing circuit for storing display data;
a first control unit for outputting address data of the first storing circuit or address data of the display data storing circuit to access to the first storing circuit or the display data storing circuit and to process the first data or the display data;
an address decoder for decoding the address data output by the first control unit to identify whether the address data indicates the first storing circuit or the display data storing circuit, outputting a first address value in cases where the address data indicates the first storing circuit, and outputting a second address value in cases where the address data indicates the display data storing circuit;
a first logical circuit, connected with the first register and the address decoder, for producing a first logical value indicating the second access mode in cases where the first register registers the access mode value indicating the first access mode and the second address value indicating the display data storing circuit is output by the address decoder;
a picture display logical circuit for accessing to the display data storing circuit to display the display data stored in the display data storing circuit on the on-screen display; and
a bus interface unit for receiving the first logical value from the first logical circuit, setting the access mode of the first control unit to the second access mode according to the first logical value to make the first control unit access to the display data storing circuit in a first half of the second bus cycle and to make the picture display logical circuit access to the display data storing circuit in a second half of the second bus cycle.
In cases where the first control unit accesses to the first storing circuit to read out or write first data from/to the first storing circuit, the first control unit can sufficiently access to the first storing circuit at the first access mode. In contrast, in cases where the first control unit accesses to the display data storing circuit to write display data to the display data storing circuit, there is a case that the picture display logical circuit accesses to the display data storing circuit simultaneously with the accessing of the first control unit to the display data storing circuit. Therefore, assuming that the first control unit accesses to the display data storing circuit at the first access mode, because the first control unit and the picture display logical circuit cannot simultaneously access to the display data storing circuit in a time-period of the first bus cycle corresponding to the first access mode, a wrong operation is performed by the microcomputer in cases where the picture display logical circuit accesses to the display data storing circuit simultaneously with the accessing of the first control unit to the display data storing circuit.
In the above configuration of the present invention, in cases where the first control unit desires to access to the display data storing circuit, the access mode is set to the second access mode by the bus interface unit, and the first control unit accesses to the display data storing circuit in a time-period of one second bus cycle longer than that of the first bus cycle. Therefore, even though the picture display logical circuit desires to access to the display data storing circuit simultaneously with the accessing of the first control unit to the display data storing circuit, the picture display logical circuit can access to the display data storing circuit, in the time-period of the second bus cycle, simultaneously with the accessing of the first control unit to the display data storing circuit.
Accordingly, because the access mode is set to the second access mode in an only case where the first control unit accesses to the display data storing circuit, and because the access mode is set to the first access mode in cases where the first control unit accesses to the first storing circuit, an wrong operation of the microcomputer based on the simultaneous accessing of the first control unit and the picture display logical circuit to the display data storing circuit can be prevented, a time-period of each accessing of the first control unit to the first storing circuit can be shortened to the time-period of the first bus cycle, and a software processing efficiency can be improved.
It is preferred that the picture display logical circuit comprises a second register for registering a display condition value indicating a display active condition or a display condition value indicating a display non-active condition,
the microcomputer further comprises
a second logical circuit for receiving the first address value or the second address data from the address decoder, receiving the display condition value from the second register, performing a logical calculation according to the first address value or the second address data and the display condition value, producing a second logical value from the first address value or the second address data and the display condition value, and outputting the second logical value to the first logical circuit,
the second logical circuit outputs the second logical value by receiving the second address value indicating the display data storing circuit from the address decoder and receiving the display condition value indicating the display active condition from the second register,
the first logical circuit outputs the first logical value indicating the second access mode by receiving the access mode value indicating the first access mode from the first register and receiving the second logical value from the second logical circuit, and
the bus interface unit sets the access mode of the first control unit to the second access mode according to the first logical value of the first logical circuit to make the first control unit access to the display data storing circuit in the first half of the second bus cycle and to make the picture display logical circuit access to the display data storing circuit in the second half of the second bus cycle.
In the above configuration, in cases where the picture display logical circuit is set to the display non-active condition, even though the first control unit outputs the address data of the display data storing circuit, because the accessing of the picture display logical circuit to the display data storing circuit is not performed in the display non-active condition, the bus interface unit sets the access mode of the first control unit to the first access mode.
In contrast, in cases where the picture display logical circuit is set to the display active condition, there is a case that the accessing of the picture display logical circuit to the display data storing circuit is performed in the display active condition. Therefore, the bus interface unit sets the access mode of the first control unit to the second access mode according to the first logical value and the second logical value in case of the accessing of the first control unit to the display data storing circuit.
Accordingly, a time-period of each accessing of the first control unit to the first storing circuit can be moreover shortened to the time-period of the first bus cycle while preventing an wrong operation of the microcomputer based on the simultaneous accessing of the first control unit and the picture display logical circuit to the display data storing circuit, and a software processing efficiency can be moreover improved.
It is also preferred that the picture display logical circuit comprises
a second register for registering a display condition value indicating a display active condition or a display condition value indicating a display non-active condition; and
a block active signal producing circuit, connected with the second register, for producing a block active signal indicating a block display time-period in the on-screen display in cases where the display condition value indicating the display active condition is registered in the second register,
the microcomputer further comprises
a second logical circuit for receiving the first address value or the second address data from the address decoder, receiving the block active signal from the block active signal producing circuit, performing a logical calculation according to the first address value or the second address data and the block active signal, producing a second logical value from the first address value or the second address data and the block active signal, and outputting the second logical value to the first logical circuit,
the second logical circuit outputs the second logical value by receiving the second address value indicating the display data storing circuit from the address decoder and receiving the block active signal indicating the block display time-period from the block active signal producing circuit,
the first logical circuit outputs the first logical value indicating the second access mode by receiving the access mode value indicating the first access mode from the first register and receiving the second logical value from the second logical circuit, and
the bus interface unit sets the access mode of the first control unit to the second access mode according to the first logical value of the first logical circuit to make the first control unit access to the display data storing circuit in the first half of the second bus cycle of the block display time-period and to make the picture display logical circuit access to the display data storing circuit in the second half of the second bus cycle of the block display time-period.
In the above configuration, in cases where the picture display logical circuit is set to the display non-active condition, even though the first control unit outputs the address data of the display data storing circuit, because the accessing of the picture display logical circuit to the display data storing circuit is not performed in the display non-active condition, the bus interface unit sets the access mode of the first control unit to the first access mode.
In contrast, in cases where the picture display logical circuit is set to the display active condition, there is a case that the accessing of the picture display logical circuit to the display data storing circuit is performed in a block display time-period of the display data. The block display time-period is indicated by the block active signal produced by the block active signal producing circuit. Therefore, the bus interface unit sets the access mode of the first control unit to the second access mode in the block display time-period according to the first logical value and the second logical value in case of the accessing of the first control unit to the display data storing circuit.
Accordingly, a time-period of each accessing of the first control unit to the first storing circuit can be moreover shortened to the time-period of the first bus cycle while preventing an wrong operation of the microcomputer based on the simultaneous accessing of the first control unit and the picture display logical circuit to the display data storing circuit, and a software processing efficiency can be moreover improved.
It is also preferred that a second logical circuit for receiving the first address value or the second address data from the address decoder, receiving a vertical synchronization signal, performing a logical calculation according to the first address value or the second address data and the vertical synchronization signal, producing a second logical value from the first address value or the second address data and the vertical synchronization signal, and outputting the second logical value to the first logical circuit,
the second logical circuit outputs the second logical value by receiving the second address value indicating the display data storing circuit from the address decoder and receiving the display condition value indicating the display active condition from the second register,
the first logical circuit outputs the first logical value indicating the second access mode by receiving the access mode value indicating the first access mode from the first register and receiving the second logical value from the second logical circuit, and
the bus interface unit sets the access mode of the first control unit to the second access mode according to the first logical value of the first logical circuit to make the first control unit access to the display data storing circuit in the first half of the second bus cycle and to make the picture display logical circuit access to the display data storing circuit in the second half of the second bus cycle.
In the above configuration, in cases where the picture display logical circuit is set to a display impossible condition indicated by the vertical synchronization signal, even though the first control unit outputs the address data of the display data storing circuit, because the accessing of the picture display logical circuit to the display data storing circuit is not performed in the display impossible condition, the bus interface unit sets the access mode of the first control unit to the first access mode.
In contrast, in cases where the picture display logical circuit is set to a display possible condition indicated by the vertical synchronization signal, there is a case that the accessing of the picture display logical circuit to the display data storing circuit is performed in the display possible condition. Therefore, the bus interface unit sets the access mode of the first control unit to the second access mode according to the first logical value and the second logical value in case of the accessing of the first control unit to the display data storing circuit.
Accordingly, a time-period of each accessing of the first control unit to the first storing circuit can be moreover shortened to the time-period of the first bus cycle while preventing an wrong operation of the microcomputer based on the simultaneous accessing of the first control unit and the picture display logical circuit to the display data storing circuit, and a software processing efficiency can be moreover improved.
Also, because no active register is required, the microcomputer can be simplified.
It is also preferred that the microcomputer further comprising a change-over switch for connecting the first control unit with the display data storing circuit in the first half of the second bus cycle and connecting the picture display logical circuit with the display data storing circuit in the second half of the second bus cycle according to a request of the display data storing circuit, in cases where the access mode of the first control unit is set to the second access mode by the bus interface unit to which the first logical value is output from the first logical circuit.
In the above configuration, even though the accessing of the first control unit to the display data storing circuit is performed simultaneously with the accessing of the picture display logical circuit to the display data storing circuit, because the change-over switch selects the first control unit and the display data storing circuit in order, the first control unit accesses to the display data storing circuit in the first half of the second bus cycle, and the display data storing circuit accesses to the display data storing circuit in the second half of the second bus cycle.
Accordingly, the simultaneous accessing of both the first control unit and the picture display logical circuit can be reliably performed without any wrong operation of the microcomputer.
It is also preferred that the first logical circuit is an OR gate, and the first logical value indicating the second access mode is xe2x80x9c1xe2x80x9d indicating a high level.
Therefore, the access mode of the first control unit can be reliably set by the bus interface unit according to the first logical value.
It is also preferred that the first logical circuit is an OR gate, the first logical value indicating the second access mode is xe2x80x9c1xe2x80x9d indicating a high level, and the second logical circuit is an AND circuit.
Therefore, the access mode of the first control unit can be reliably set by the bus interface unit according to the first and second logical values.